1. Field of the Invention
The present invention relates generally to a semiconductor device, and more specifically to a semiconductor device including an interlayer insulating film having higher crack resistance and insulation. The present invention further relates to a method of manufacturing such a device.
2. Description of the Background Art
Recently, in the field of manufacturing large scale integrated circuit devices (hereinafter referred to as LSI devices), mass production of 4M bit DRAMs has been practiced on a full scale. Miniaturizing LSI devices requires miniaturization of interconnection widths, interconnection spaces, etc., resulting in increase in steps formed on the surface of a substrate. The increase of steps formed on the surface of the substrate results in the following problems. Referring to FIG. 7, a first interconnection pattern 52 is provided on a substrate 51. The first interconnection pattern 52 has a number of stepped portions 52a. An interlayer insulating film 53 is provided covering the first interconnection pattern 52.
Affected by the stepped portions 52a of the first interconnection pattern 52, the surface of the interlayer insulating film 53 is unevenly shaped. Forming a second interconnection pattern 54 on the unevenly shaped surface of the interlayer insulating film 53 gives rise to formation of a narrow portion 54A to the second interconnection patter 54. The narrow portion A can result in disconnection. Also, patterning does not proceed in an accurate manner in forming the second interconnection pattern 54, with the surface of the interlayer insulating film 53 being unevenly shaped. Consequently, the residue of material forming the interconnection pattern remains in areas other than intended, resulting in shorting.
Various planar techniques have been proposed for flattening interlayer insulating films in order to solve this problem. However, no definitely effective and efficient process has been discovered yet at present.
FIGS. 6A-6C are sectional views showing a conventional process of a planar technique for flattening interlayer insulating films (Semicon News June, 1989).
Referring to FIG. 6A, a semiconductor substrate 1 having a stepped pattern 2. A silicon oxide film 3 (hereinafter plasma oxide film 3) is formed to cover the surface of the stepped pattern 2 by plasma chemical vapor deposition (hereinafter plasma CVD). The thickness of the plasma oxide film 3 is between about 0.1-0.3 .mu.m. The plasma oxide film 3 is formed using silane (SiH.sub.4)/nitrous oxide (N.sub.2 O) or tetra-ethyl-ortho-silicate (TEOS)/oxygen O.sub.2 as a material gas. The plasma oxide film 3 is superior in insulation and crack resistance, but on the other hand is inferior in step coverage and filling of recesses.
Referring to FIG. 6B, a silicon oxide film 4 (hereinafter atmospheric pressure TEOS oxide film 4) is deposited by atmospheric pressure CVD using TEOS/ozone (O.sub.3), so as to cover the stepped pattern 2, filling up the recesses of the stepped pattern 2. The atmospheric pressure TEOS oxide film 4 has a thickness in the range of approximately 0.6-0.8 .mu.m in the step 2a of the stepped pattern 2. The plasma oxide film 3 plus the atmospheric pressure TEOS oxide film 4 equals approximately 0.9 .mu.m in film thickness.
Referring to FIG. 6C, a spin on glass film 5 (hereinafter SOG film 5) is applied onto the atmospheric pressure TEOS oxide film 4 so as to fill up recess 4a existing on the surface of the atmospheric pressure TEOS oxide film 4 and to cover the atmospheric TEOS oxide film 4, and annealing is performed thereon. Thereafter, the SOG film 5 is etched in such a manner that the SOG film 5 remains only in the recess 4a of the atmospheric pressure TEOS oxide film 4. A three-layer structured interlayer insulating film 24 is thus formed on the semiconductor substrate 1.
The manufacturing process of a conventional interlayer insulating film is composed as described above. The plasma oxide film 3 formed by the above-mentioned method is superior in insulation and crack resistance compared to the atmospheric TEOS oxide film 4. The plasma oxide film 3 does not easily change its film characteristics by heat-treatment. Even with the difference in shrinkage factors between the stepped pattern 2 (an aluminum interconnection which is an underlying step) and the atmospheric pressure TEOS oxide film 4, cracks in the atmospheric pressure TEOS oxide film 4 due to the difference can be prevented by using the plasma oxide film 3 as the underlying film of the atmospheric pressure TEOS oxide film 4.
The atmospheric pressure TEOS oxide film 4 is superior in step coverage and filling of recesses. The atmospheric pressure TEOS oxide film 4 fills up very small trenches completely which may produce voids if the plasma oxide film 3 is used.
Neither the plasma oxide film 3 nor the atmospheric pressure TEOS oxide film 4 is independently suitable as an interlayer insulating film. The combination of these two kinds of films permits the advantages of these films to be united, thereby forming a superior interlayer insulating film.
In the above conventional example, referring to FIG. 6C, the interlayer insulating film is not flat enough at a wide trench 2a, and, therefore, the SOG film 5 fills the recess 4a of the atmospheric pressure TEOS oxide film 4. The flatness of the surface of the interlayer insulating film is improved by filling the recesses 4a with the SOG film 5.
In the conventional interlayer insulating film thus structured, referring to FIG. 6C, cracks are produced in the SOG film 5 or the atmospheric pressure TEOS oxide film 4 in the process of annealing the SOG film 5 formed last, or in a subsequent heat treatment process, because of the difference in shrinkage factors between the SOG film 5 and the atmospheric pressure TEOS oxide film 4.
The cracks produced in the SOG film 5 and atomospheric TEOS oxide film 4 cause the problems as below.
Referring to FIG. 8, with a crack 60 formed in the SOG film 5 and TEOS oxide film 4, Al enters the crack 60 at the time of sputtering for forming a second Al interconnection 25.
Also, if the crack 60 is too large, the second Al interconnection 25 is formed with a part disconnected as shown in FIG. 8. The residue left behind at the time of etching the second Al interconnection 25 remains along the crack 60, causing shorting.